1. Field of the Invention
The present invention relates to the field of microwave circuits, and more particularly, to testing of monolithic microwave integrated circuits and other active and passive microwave components.
2. Background Information
Microwave systems are often composed of monolithic microwave integrated circuits (MMICs), other active microwave devices such as GaAs transistors, passive microwave components and other non-microwave components such as logic and control structures.
A monolithic microwave integrated circuit or MMIC is an integrated circuit which is designed to operate at microwave frequencies. MMICs are normally fabricated in GaAs because of the much higher potential operating frequency which GaAs provides as compared to silicon. A typical MMIC may include one or more amplifiers, some passive components and one or more feedback loops which provide feedback from the output of an amplifier or circuit to its input to establish a desired transfer function for that circuit.
It is known in the art to fabricate microwave systems from a variety of such components by providing a ceramic substrate having microstrip RF circuitry, DC supply lines (conductors), logic lines, control lines and contact pads fabricated thereon and by attaching devices and components such as MMICs, GaAs transistors, other microwave and supporting components to the substrate and connecting them to the circuitry on the substrate using wire bonds or tab interconnections.
Such fabrication techniques have a number of disadvantages. Thin and thick film methods of fabricating circuitry on ceramic substrates have tolerance limitations which prevent such structures from being produced with microwave characteristics which are repeatable with close tolerances. Consequently, there is substrate-to-substrate variation in the microwave characteristics of such nominally identical substrates. Further, the active microwave components such as MMICs and GaAs transistors themselves have fabrication tolerances which result in variations in operating characteristics from device to device. Further, in such structures, impedance discontinuities and mismatches are normal at the edges of MMICs and GaAs transistors. These impedance discontinuities vary with the actual placement of the chips on the surface of or in cavities in the ceramic substrate. This is because slight changes in the positioning of such devices change both the lengths of the gaps between the device and the substrate and the alignment of the device structure with the substrate structure. Further, these physical assembly tolerances result in variable interconnect bond lengths and configurations, resulting in varied electrical reactance and consequently, varied circuit performance. These impedance mismatches also vary with actual component and substrate impedance values. Further, these and other fabrication-tolerance-induced differences in impedances result in reflections and other undesirable operational effects which degrade system operating characteristics. The cumulative effect of these differences is a wide range of system operating characteristics. Consequently, assembly of a microwave system from such components is a relatively low yield process in which many of the resulting systems do not meet specifications. A significant contributor to this low yield is the fact that many active microwave components cannot readily be accurately tested over their full expected operating frequency and power ranges in a non-destructive manner because of the difficulty of coupling such components to a test system. Consequently, many components which pass preassembly testing do not in reality meet specifications.
As the desired operating frequency of such microwave systems has increased from the neighborhood of 2-GHz to still higher frequencies in the range from 8 GHz to 16 GHz, or more, the problem of thin film and thick film fabrication tolerances and component testing have become ever more vexing.
Many MMICs and other active microwave devices include delicate structures which can easily be damaged or destroyed. These include conductors which are spaced from the surface of the GaAs by an air gap--a structure which is known as an "air bridge". Air bridges are used in these MMICs in order to provide the MMIC with particular desired operational characteristics. These delicate structures severely limit the assembly techniques which can be used to connect these devices into microwave systems. Further, such components are quite sensitive to the placement near their surfaces of conductors or dielectric materials having dielectric constants of more than one, especially in the vicinity of inductors, air bridges and field effect device gate regions.
In digital systems, individual chips can be extensively tested using wafer probe and other test systems before being committed to assembly into individual packages. After packaging, they can be further tested prior to assembly into a system. As a result, yield at system assembly is normally quite high. It is this assurance of successful assembly of digital components into an operative final system which has made feasible the provision of microcomputers and other digital systems at cost-for-performance prices which were unimaginable a decade ago.
Such pre-packaging has been impossible with active microwave devices because the losses and other penalties which packaging introduces are worse than the disease packaging would be intended to cure. Consequently, for microwave systems, post-packaging testing is not available at a component level as a final-assembly-yield-enhancement mechanism. Even full testing of components at a wafer level is not normally feasible because of the relatively large probe which is needed to provide an impedance match to the MMICs or other devices under test. However, the problem of low final yield has led to the design of some active microwave components for testing with so-called co-planar probe such as those built by Cascade Microtech. This requires that the chips be made over-sized in order to provide space on their upper surface for a microwave port having a signal conductor in the middle and two true ground conductors symmetrically disposed on opposite sides of that signal conductor. This structure is required for a co-planar probe to be connected to this microwave port in a well-matched, repeatable manner. The provision of a true ground on the upper surface of a microwave chip is not a simple matter at microwave frequencies (unlike the situation with digital chips which typically operate at frequencies of less than 50 MHz). Generally, this requires the use of a metal connection between the front and back surfaces of the chip. Such metal connections can be provided by plated through holes, but the provision of plated through holes increases the complexity of the fabrication process and decreases yield. Even those chips which are designed for co-planar probing cannot be tested at full power across their full operative range with a co-planar probe prior to die attach because of the poor thermal conductivity of MMICs. Consequently, design of a microwave device for co-planar probing has its own associated penalties such as increased size, increased process complexity, lower process yield and still suffers from a lack of complete assurance that test results will correlate with system performance.
A significant problem with the low yield of fully assembled systems is that such structures cannot be effectively reworked to replace faulty components because the component's connections cannot be removed in a non-destructive manner. Consequently, systems which are out of specification when assembled must be scrapped. Alternatively, if the microwave module is designed to allow rework, rework-induced damage is common, with a consequent limited rework-induced increase in yield.
Thus, there is a continuing need for a microwave fabrication process which enables passive components to be fabricated with highly repeatable characteristics and which enables pre-testing of active devices and/or the removal and replacement of faulty components without impairing any good components when a system fails to meet specifications.
Because of the low yield of finally assembled microwave systems, such systems are quite expensive both because of ultimate component cost and because the fabrication process is more akin to engineering than to semiconductor fabrication techniques. In order to increase the yield of final systems and to reduce their cost to the point where they become feasible for use in everyday systems, there is a need for a technique for testing individual microwave components and subsystems in an efficient, high yield manner which enables such components and subsystems to be assembled into final systems with a high yield.
A substantial problem with presently available techniques for testing monolithic microwave integrated circuits (MMICs) is that test results do not correlate well with the component's operation when assembled into a system. This has a number of causes. One is that much testing is done at DC rather than at microwave frequencies because of the problems of providing good microwave coupling between a test system and a MMIC. Another is the requirement that microwave components be made oversized in order to provide a well matched coupling between the component and a test system--a requirement which makes testing much less attractive than it could be. Further, because of the poor thermal conductivity of a MMIC and the inability of test fixtures to carry away the heat generated, full power, full frequency testing of such components is not feasible even with oversized components designed for connection to a test probe. Further, the component to be tested cannot be connected to the test system in the same way in which it will be ultimately connected into a system because such system connections are permanent and not reworkable. Consequently, there is a poor correlation between test measurements and the system performance of components even when the tradeoff decisions are made in favor of testing. Consequently, there is a need for a microwave test technique and system which enables microwave components to be fully tested, both in power and frequency, without requiring that the components be fabricated oversized to facilitate such testing and which provides high correlation between test results and subsequent system performance of those tested components.
A high density interconnect (HDI) structure or system which has been developed by General Electric Company offers many advantages in the compact assembly of digital and other electronic systems. For example, an electronic system such as a microcomputer which incorporates between 30 and 50 chips can be fully assembled and interconnected on a single substrate which is 2 inches long by 2 inches wide by 0.050 inch thick. The maximum operating frequency of such systems is normally, at present, less than about 50 MHz. Even more important than the compactness of this high density interconnect structure is the fact that it can be disassembled for repair or replacement of a faulty component and then reassembled without significant risk to the good components incorporated within the system. This reworkability or repairability is a substantial advance over prior connection systems in which reworking the system to replace damaged components was either impossible or involved substantial risk to the good components.
Briefly, in this high density interconnect structure, a ceramic (or compatible metal) substrate such as alumina which may be 25-100 mils thick and of appropriate size and strength for the overall system, is provided. This size is typically less than 2 inches square. Once the position of the various chips has been specified, individual cavities or one large cavity having appropriate depths at the intended locations of the various chips are prepared. This may be done by starting with a bare substrate having a uniform thickness and the desired size. Conventional, laser or ultrasonic milling may be used to form the cavities in which the various chips and other components will be positioned. For many systems where it is desired to place chips edge-to-edge, a single large cavity is satisfactory. That large cavity may typically have a uniform depth where the semiconductor chips have a substantially uniform thickness. Where a particularly thick or a particularly thin component will be placed, the cavity bottom must be made respectively deeper or shallower to place the upper surface of that component in substantially the same plane as the upper surface of the rest of the components and the surface of the portion of the substrate which surrounds the cavity. The bottom of the cavity is then provided with a thermoplastic adhesive layer which may preferably be polyetherimide resin available under the trade name ULTEM.RTM. from the General Electric Company. The various components are then placed in their desired locations within the cavity, the entire structure is heated to the softening point of the ULTEM.RTM. polyetherimide (in the vicinity of 217.degree. C. to 235.degree. C. depending on the formulation used) and then cooled to thermoplastically bond the individual components to the substrate. At this stage, the upper surfaces of all components and the substrate are disposed in substantially a common plane. Thereafter, a polyimide film which may be Kapton.RTM. polyimide, available from E. I. du Pont de Nemours Company, which is about 0.0005-0.003 inch (12.5-75 microns) thick is pretreated to promote adhesion and coated on one side with an ULTEM.RTM. polyetherimide resin or another thermoplastic and laminated across the top of the chips, other components and the substrate with the ULTEM.RTM. resin serving as a thermoplastic adhesive to hold the Kapton.RTM. in place. Thereafter, via holes are laser drilled in the Kapton.RTM. and ULTEM.RTM. layers in alignment with the contact pads on the electronic components to which it is desired to make contact. A metallization layer which is deposited over the Kapton.RTM. layer extends into the via holes and makes electrical contact to the contact pads disposed thereunder. This metallization layer may be patterned to form individual conductors during the process of depositing it or may be deposited as a continuous layer and then patterned using photoresist and etching. The photoresist is preferably exposed using a laser which is scanned relative to the substrate to provide an accurately aligned conductor pattern at the end of the process.
Additional dielectric and metallization layers are provided as required in order to provide all of the desired electrical connections among the chips. Any misposition of the individual electronic components and their contact pads is compensated for by an adaptive laser lithography system which is the subject of some of the U.S. Patents and Patent Applications which are listed hereinafter.
This high density interconnect structure, methods of fabricating it and tools for fabricating it are disclosed in U.S. Pat. No. 4,783,695, entitled "Multichip Integrated Circuit Packaging Configuration and Method" by C. W. Eichelberger, et al.; U.S. Pat. No. 4,835,704, entitled "Adaptive Lithography System to Provide High Density Interconnect" by C. W. Eichelberger, et al.; U.S. Pat. No. 4,714,516, entitled "Method to Produce Via Holes in Polymer Dielectrics for Multiple Electronic Circuit Chip Packaging" by C. W. Eichelberger, et al.; U.S. Pat. No. 4,780,177, entitled "Excimer Laser Patterning of a Novel Resist" by R. J. Wojnarowski et al.; U.S. patent application Ser. No. 249,927, now abandoned filed Sep. 27, 1988, entitled "Method and Apparatus for Removing Components Bonded to a Substrate" by R. J. Wojnarowski, et al.; U.S. patent application Ser. No. 310,149, filed Feb. 14, 1989, now U.S. Pat. No. 4,894,115, issued Jan. 16, 1991 entitled "Laser Beam Scanning Method for Forming Via Holes in Polymer Materials" by C. W. Eichelberger, et al.; U.S. patent application Ser. No. 312,798, now abandoned filed Feb. 21, 1989, entitled "High Density Interconnect Thermoplastic Die Attach Material and Solvent Die Attachment Processing" by R. J. Wojnarowski, et al.; U.S. patent application Ser. No. 283,095, filed Dec. 12, 1988, now U.S. Pat. No. 4,878,991, issued Nov. 7, 1989 entitled "Simplified Method for Repair of High Density Interconnect Circuits" by C. W. Eichelberger, et al.; U.S. patent application Ser. No. 305,314, filed Feb. 3, 1989, abandoned in favor of continuation application Ser. No. 559,532, filed Jul. 19, 1990 entitled "Fabrication Process and Integrated Circuit Test Structure" by H. S. Cole, et al.; U.S. Pat. No. 5,019,946, filed Sep. 27, 1988, entitled "High Density Interconnect With High Volumetric Efficiency" by C. W. Eichelberger, et al.; U.S. Pat. No. 5,019,535, filed Mar. 28, 1989, entitled "Die Attachment Method for Use in High Density Interconnected Assemblies" by R. J. Wojnarowski, et al.; U.S. patent application Ser. No. 253,020, filed Oct. 4, 1988, now U.S. Pat. No. 4,960,613, issued Oct. 2, 1990 entitled "Laser Interconnect Process" by H. S. Cole, et al.; U.S. patent application Ser. No. 230,654, filed Aug. 5, 1988, now U.S. Pat. No. 4,884,122, issued Nov. 28, 1989 entitled "Method and Configuration for Testing Electronic Circuits and Integrated Circuit Chips Using a Removable Overlay Layer" by C. W. Eichelberger, et al.; U.S. patent application Ser. No. 233,965, filed Aug. 18, 1988, now abandoned entitled "Direct Deposition of Metal Patterns for Use in Integrated Circuit Devices" by Y. S. Liu, et al.; U.S. Patent application Ser. No. 237,638, filed Aug. 23, 1988, now U.S. Pat. No. 4,882,200, issued Nov. 21, 1989 entitled "Method for Photopatterning Metallization Via UV Laser Ablation of the Activator" by Y. S. Liu, et al.; U.S. patent application Ser. No. 237,685, filed Aug. 25, 1988, now abandoned entitled "Direct Writing of Refractory Metal Lines for Use in Integrated Circuit Devices" by Y. S. Liu, et al.; U.S. patent application Ser. No. 240,367, filed Aug. 30, 1988, now U.S. Pat. No. 4,933,042, issued Jun. 12, 1990 entitled "Method and Apparatus for Packaging Integrated Circuit Chips Employing a Polymer Film Overlay Layer" by C. W. Eichelberger, et al.; U.S. patent application Ser. No. 342,153, filed Apr. 24, 1989, now U.S. Pat. No. 4,897,153, issued Jan. 30, 1990 entitled "Method of Processing Siloxane-Polyimides for Electronic Packaging Applications" by H. S. Cole, et al.; U.S. patent application 289,944, filed Dec. 27, 1988, now U.S. Pat. 4,988,412, issued Jan. 29, 1991 entitled "Selective Electrolytic Deposition on Conductive and Non-Conductive Substrates" by Y. S. Liu, et al.; U.S. patent application Ser. No. 312,536, filed Feb. 17, 1989, now abandoned entitled "Method of Bonding a Thermoset Film to a Thermoplastic Material to Form a Bondable Laminate" by R. J. Wojnarowski; U.S. patent application Ser. No. 363,646, now abandoned filed Jun. 8, 1989, entitled "Integrated Circuit Packaging Configuration for Rapid Customized Design and Unique Test Capability" by C. W. Eichelberger, et al.; U.S. Pat. No. 07/459,844, filed Jan. 2, 1990, entitled "Area-Selective Metallization Process" by H. S. Cole, et al.; U.S. Pat. No. 5,258,920, filed Dec. 26, 1989, entitled "Locally Orientation Specific Routing System" by T. R. Hallet, et al.; U.S. Pat. No. 5,169,678, filed Dec. 26, 1989, entitled "Laser Ablatable Polymer Dielectrics and Methods" by H. S. Cole, et al.; U.S. patent application Ser. No. 454,546, now abandoned filed Dec. 21, 1989, entitled "Hermetic High Density Interconnected Electronic System" by W. P. Kornrumpf, et al.; U.S. Pat. No. 5,040,047 filed Dec. 26, 1989, entitled "Enhanced Fluorescence Polymers and Interconnect Structures Using Them" by H. S. Cole, et al.; and U.S. patent application Ser. No. 454,545, filed Dec. 21, 1989, abandoned in favor of divisional application Ser. No. 646,112, filed Jan. 28, 1991 entitled "An Epoxy/Polyimide Copolymer Blend Dielectric and Layered Circuits Incorporating It" by C. W. Eichelberger, et al. Each of these Patents and Patent Applications is incorporated herein by reference.
This high density interconnect system has been developed for use in interconnecting semiconductor chips to form digital systems. That is, for the connection of systems whose operating frequencies are typically less than about 50 MHz, which is low enough that transmission line and other wave impedance matching effects have not needed to be considered.
The interconnection of microwave structures presents many problems, considerations and challenges not faced in the interconnection of digital systems. Use of microwave frequencies requires consideration of wave characteristics, transmission line effects, material properties at microwave frequencies, the presence of exposed delicate structures on MMICs and other components and system and component characteristics which do not exist at the lower operating frequencies of such digital systems. These considerations include the question of whether the dielectric materials are suitable for use at microwave frequencies, since materials which are good dielectrics at lower frequencies can be quite lossy or even conductive at microwave frequencies. Further, even if the dielectric is not lossy at microwave frequencies, its dielectric constant itself may be high enough to unacceptably modify the operating characteristics of MMICs, GaAs transistors and other microwave components or structures which might be interconnected using a high density interconnect structure. Since the first dielectric layer of this high density interconnect structure is applied by a lamination process involving the application of substantial pressure to the polyimide film, there is a substantial concern that air bridges and other delicate structures in microwave components may be damaged, destroyed or modified either by the lamination pressure causing them to collapse or by the infiltration of the thermoplastic adhesive into the air gap under the conductor, thereby modifying the dielectric properties of that gap, or even the mere presence of the dielectric unacceptably modifying the operating characteristics of some of the components.
The related application Ser. No. 17/504,821 now abandoned overcomes the problems of reworkability and poor passive component tolerances of the prior art thin and thick film microwave system assembly methods whereby if a microwave system, when assembled does not meet specifications, it can be disassembled for removal of faulty components and reassembled without danger to good components.
Related U.S. Pat. No. 5,206,712 provides a solution to the problem of packaging microwave components in an efficient, reliable, high yield manner which makes the assembly of a microwave system from prepackaged components attractive and desirable, both from an efficiency and yield point of view.
A technique and system for testing microwave components is needed which provides a high correlation between the results of component testing and the performance of systems assembled from tested components in order to facilitate the provision of high yield, low cost microwave system assembly.